Modern speech communication systems, such as common carrier telephone systems, digitally encode analog speech signals for transmission as a digital signal. At the receiving end of the communication system, the digital signal is used to reconstruct the analog speech signal. The communication system must be able to reconstruct the speech signal at a quality that is intelligible at the receiving station.
An analog speech signal has a characterisitc of continuously varying amplitude with time. The rate at which the analog speech signal is sampled for digital encoding has an effect on the ability of the system to reconstruct the analog signal from the digital signal generated in the encoding process. Theoretically, for standard pulse code modulation the encoding and recovery process can be accomplished without substantially impairing the reconstructed analog signal if the rate at which samples are taken is at least twice the rate of the highest frequency component of the analog signal, that is, at the Nyquist rate. For high quality reconstruction of the analog signal, an even higher encoding rate is needed. The rate at which the analog signal is sampled is called the sampling rate of the encoding scheme. The corresponding bit rate of the communication link is a function of the sampling rate and the number of quantization bits per sample in the encoding scheme.
Thus for high quality reconstruction of the speech signal at the receiving station, a high bit rate is necessary. However a high bit rate digital signal requires a correspondingly wide bandwidth for transmission. So in order to maximize the utilization of a given communication system, a lower bit rate is desirable.
Several schemes are under investigation for lower bit rate encoding of analog speech data without sacrificing quality of the speech reconstructed at the receiving station. One technique is termed adaptive delta modulation or continuously variable slope delta modulation (CVSD).
The CVSD technique offers nearly the same voice quality as standard 64 kilobit pulse code modulation using only half of the digital bandwidth required for the standard systems. See, "lowering PCM Encoding Rates Provides More Channels", TELEPHONY, Sept. 12, 1983, pp. 34-48.
A CVSD encoder operates by comparing the received analog signal with the signal that has been reconstructed from the digital output of the encoder. When the incoming analog signal is at a level less than the reconstructed signal, then the digital output is set at a first value in response to a clock. When the incoming analog signal is greater than the reconstructed signal, then the digital output is set at another value in response to the clock.
The analog signal is reconstructed from the digital signal by supplying the digital signal to an integrator with a continuously variable slope. The continuously variable slope is caused in response to an algorithm which detects the occurrence of either a series of three or four consecutive ones or a series of three or four consecutive zeros in the digital signal. Upon the occurrence of either of those events, the slope is adjusted in order to attempt to track the incoming analog signal more closely.
More information about a particular CVSD encoder can be found in Motorola, Inc.'s product literature for the MC3417, MC3418, MC3417, MC3518 chip family. See, LINEAR AND INTERFACE INTEGRATED CIRCUITS, Motorola, 1983, Series D, pp. 9-12 et. seq.
FIG. 1 is a graph illustrating the digital encoding of an analog signal according to the CVSD technique. The analog signal 10 shown as a sinusoid. The digital encoded signal is shown at 11. And the reconstructed signal output from the integrator of the CVSD apparatus is shown at 12. As can be seen, the digital output 11 is high when the reconstructed signal 12 is at a level below the incoming analog signal 10. When the reconstructed signal 12 crosses the analog signal 10, such as at point 13, the digital signal 11 swings low on the next clock. This causes the sign of the slope of the reconstructed signal 12 from the integrator to reverse as shown along the segment 14. At the next clock cycle, the comparator will indicate that the analog signal 10 is above the reconstructed signal 12 once again and swing the digital output high at point 15 which reverses the sign of the slope of the reconstructed signal. This process continues for each clock cycle.
As can be seen in FIG. 1, the CVSD technique provides relatively close approximation of the analog signal input. However, the level tracking of the CVSD output signal 11 is relatively poor. Likewise the response of the CVSD digital output signal 11 to fast changes in the analog signal 10 is relatively poor.